A01 Co-design of Area-Dependent VCM Cell Arrays and CMOS Circuits for In-Memory Computing
Sketch of the co-design of area-dependent heterostructure devices and CMOS circuits for in-memory computing. In Phase 1, 2D cross-bar arrays will be addressed. In the subsequent phases, the extension to 3D arrays is envisioned.
When using memory cells to perform logic calculations or vector-matrix multiplication it is important to have an analog switching capability. This project will make analog switching elements available that can be integrated on top of a CMOS circuit. We will develop non-filamentary VCM cells with both analog switching and very low current levels. The latter is highly advantageous in terms of suppressing parasitic effects in dense structures and significantly reducing power consumption. We will co-design the devices and the CMOS circuitry at an early stage.
Current-voltage curve of PCMO/AlOx /Al devices with different area; (b) Scaling of the device resistance with the area from μm to nm scale; (c) Potentiation and Depression curves of PCMO/AlOx /Al devices for different pulse height [Gut+21]; (d) Current-voltage curve of a PCMO device; (e) The regions where no switching takes place are fitted by a two-resistor model with exponentially voltage-dependent resistance. In order to extract the dynamics the fitting procedure has been performed for different stop voltages; (f) The results from the fits in (d)/(e) are extrapolated to the whole voltage regime and implemented in Cadence
Sketch of the co-design of area-dependent heterostructure devices and CMOS circuits for in-memory computing. In Phase 1, 2D cross-bar arrays will be addressed. In the subsequent phases, the extension to 3D arrays is envisioned.
